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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">MPAMF_ECR, MPAM Error Control Register</h1><p>The MPAMF_ECR characteristics are:</p><h2>Purpose</h2>
        <p>MPAMF_ECR is a 32-bit read/write register that controls MPAM error interrupts for this MSC. </p>

      
        <p>MPAMF_ECR_s controls Secure MPAM error handling. 
MPAMF_ECR_ns controls Non-secure MPAM error handling.
MPAMF_ECR_rt controls Root MPAM error handling.
MPAMF_ECR_rl controls Realm MPAM error handling.</p>
      <h2>Configuration</h2><p>The power domain of MPAMF_ECR is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.
    </p><p>This register is present only when FEAT_MPAM is implemented. Otherwise, direct accesses to MPAMF_ECR are <span class="arm-defined-word">RES0</span>.</p>
        <p>If an MSC cannot encounter any of the error conditions listed in <span class="xref">'Errors in MSCs' in Arm® Architecture Reference Manual Supplement, Memory System Resource Partitioning and Monitoring (MPAM), for Armv8-A (ARM DDI 0598)</span>, both the <a href="ext-mpamf_esr.html">MPAMF_ESR</a> and MPAMF_ECR must be RAZ/WI.</p>

      
        <p>The power and reset domain of each MSC component is specific to that component.</p>
      <h2>Attributes</h2>
        <p>MPAMF_ECR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="31"><a href="#fieldset_0-31_1">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">INTEN</a></td></tr></tbody></table><h4 id="fieldset_0-31_1">Bits [31:1]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-0_0">INTEN, bit [0]</h4><div class="field">
      <p>Interrupt Enable.</p>
    <table class="valuetable"><tr><th>INTEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>MPAM error interrupts are not signaled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>MPAM error interrupts are signaled.</p>
        </td></tr></table></div><h2>Accessing MPAMF_ECR</h2>
        <p>This register is within the MPAM feature page memory frames.</p>

      
        <p>In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:</p>

      
        <ul>
<li>MPAMF_ECR_s must only be accessible from the Secure MPAM feature page.
</li><li>MPAMF_ECR_ns must only be accessible from the Non-secure MPAM feature page.
</li><li>MPAMF_ECR_rt must only be accessible from the Root MPAM feature page.
</li><li>MPAMF_ECR_rl must only be accessible from the Realm MPAM feature page.
</li></ul>

      
        <p>MPAMF_ECR_s, MPAMF_ECR_ns, MPAMF_ECR_rt, and MPAMF_ECR_rl must be separate registers:</p>

      
        <ul>
<li>The Secure instance (MPAMF_ECR_s) accesses the error interrupt controls used for Secure PARTIDs.
</li><li>The Non-secure instance (MPAMF_ECR_ns) accesses the error interrupt controls used for Non-secure PARTIDs.
</li><li>The Root instance (MPAMF_ECR_rt) accesses the error interrupt controls used for Root PARTIDs.
</li><li>The Realm instance (MPAMF_ECR_rl) accesses the error interrupt controls used for Realm PARTIDs.
</li></ul>
      <h4>MPAMF_ECR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_s</td><td><span class="hexnumber">0x00F0</span></td><td>MPAMF_ECR_s</td></tr></table><p>Accesses on this interface are <span class="access_level">RW</span>.</p><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_ns</td><td><span class="hexnumber">0x00F0</span></td><td>MPAMF_ECR_ns</td></tr></table><p>Accesses on this interface are <span class="access_level">RW</span>.</p><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_rt</td><td><span class="hexnumber">0x00F0</span></td><td>MPAMF_ECR_rt</td></tr></table><p>When FEAT_RME is implemented, accesses on this interface are <span class="access_level">RW</span>.</p><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>MPAM</td><td>MPAMF_BASE_rl</td><td><span class="hexnumber">0x00F0</span></td><td>MPAMF_ECR_rl</td></tr></table><p>When FEAT_RME is implemented, accesses on this interface are <span class="access_level">RW</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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